XMC Successfully Develops a Three-wafer Stacking Technology

XMC Launches a Wafer-level 3D IC Technology that Realizes Three-wafer Stacked Bonding

On December 3, 2018, Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. ("XMC"), a leading enterprise in semiconductor R&D and manufacturing, announced the successful development of a three-wafer stacking technology based on its 3D IC technology platform.

XMC's wafer-level 3D IC technology enables direct bonding of three wafers with different functions (such as logic, memory, and sensor) and electrical interconnection between metal layers of the different wafers. Wafer-level 3D IC technology, compared with traditional 2.5D chip stacking, can simultaneously increase bandwidth and reduce latency, leading to higher performance and lower power consumption.

Sun Peng, Vice President of Technology at XMC, said, "The 3D IC technology marks the third technology platform of XMC, following NOR Flash and MCU. XMC's 3D IC technology which is internationally advanced and domestically leading, has six years of mass production experience and can provide customers with wafer-level 3D IC foundry solutions with advanced process and flexible design." XMC started to develop 3D IC technology in 2012, successfully applied 3D IC technology to back-illuminated image sensors in 2013 with the yield of 99%, and then successively launched through-silicon via (TSV) stacking technology, hybrid bonding technology, and multi-wafer stacking technology.

The wafer-level 3D IC technology provides new solutions for chip design and manufacturing in the post-Moore era and has extensive application prospects in the fields of AI and IoT where bandwidth, performance, and multi-function integration are important requirements.