3D IC Platform
XMC 3DLink™ Technology Platform S-stacking® M-stacking® Hi-stacking™

XMC 3DLink™ Technology Platform

XMC 3DLink™ is an industry's leading 3D IC technology platform which enables direct bonding of multiple wafers or wafers to chips in a vertical direction utilizing semiconductor nanoscale-interconnection technology. This platform includes three technology categories, two-wafer stacking technology (S-stacking®), multi-wafer stacking technology (M-stacking®) and heterogeneous integration technology (Hi-stacking™). Among them, S-stacking® is mainly used in fields such as sensors (CIS, ToF), high-speed computing and in-storage computing, and M-stacking® is mainly for high-bandwidth memory, etc. After years of experience in R&D and mass production, XMC has built up a stable and reliable wafer-level 3D stacking process platform. Meanwhile, XMC plans to develop heterogeneous integration technology (Hi-stacking™) which can be applied for bonding with different die sizes or substrate materials.

In addition to significantly reducing chip size and achieving wafer-level interconnection, XMC 3DLink™ technology can improve chip performance with faster I/O speed, higher bandwidth, lower latency and lower power consumption, providing a powerful solution for chips of sensor, high-speed computing and HBM, etc.

XMC 3DLink™ Technology Highlights

- Nearly 10 years of technology experience
- 400+ independent innovation patents
- 99.9% bonding yield
- Meet JEDEC standard
- Complete design kits to support customized development
- High added-value for middle and high-end markets
- The world's unique million-level connection density
- World-class multi-wafer stacking process

XMC S-stacking® Technology

XMC S-stacking® technology enables direct bonding of two wafers in a vertical direction utilizing semiconductor nanoscale-interconnection technology.

In addition to significantly reducing chip size and achieving wafer-level interconnection, this technology can improve chip performance with faster I/O speed, higher bandwidth, lower latency and lower power consumption.

XMC S-stacking® technology was successfully developed in 2016, till now XMC has accumulated world-leading mass production experience and technical capabilities. It has been successfully applied in high-speed computing, 3D depth sensors (ToF), 3D stacked memory and other fields, bringing excellent product performance and user experience to customers.

XMC M-stacking® Technology

XMC M-stacking® technology adopts a bumpless process to enable Cu-Cu interconnection of multiple wafers and lower interconnection resistance, which is a breakthrough over the traditional package-level Micro-bump interconnection architecture. This technology has achieved higher interconnection density and alignment accuracy with bonding yield of 99.5%.

Compared with traditional HBM, wafer-level stacking increases the bandwidth by 20 times and reduces the chip thickness by 40%.

XMC completed the process verification of three-wafer stacking technology at the end of 2018, and successfully developed five-wafer stacking process in 2020. XMC M-stacking® technology provides a new solution for high-bandwidth memory, wafer Level HBM. This technology will provide more flexible and extensive options for applications such as data centers, high-speed computing, and IoT.

XMC Hi-stacking™ Technology

XMC plans to develop Hi-stacking™, a 3D heterogeneous integration technology with more flexible design and process solutions.

Unlike traditional package-level interconnection architecture, XMC Hi-stacking™ technology can provide heterogeneous integration solutions for different die sizes or substrate materials, enabling stacking with more flexibility while achieving higher yield of stacked product and lower costs.

XMC 3D heterogeneous integration technology (Hi-stacking™) can multiply the product’s memory density and communication bandwidth. It will serve the IoT, etc. markets that has a very high requirement for multi-module heterogeneous system integration with high-performance and low-power.