In the field of 3D IC, XMC's wafer-level 3D IC technology enables stacking of carriers or functional wafers vertically or stack chips with wafers, and direct electrical interconnections between layers through processes such as through-silicon via (TSV) and hybrid bonding.

The Company which accumulated many years of experience in mass production, has successfully built the wafer-level 3D IC platform with advanced technology and flexible design, covering two-wafer stacking, multi-wafer stacking, chip-wafer heterogeneous integration, and 2.5D Interposer. The platform would be able to boost the interconnection density and shorten the interconnection length between chips, better reduce latency, increase the transmission bandwidth, meet the requirements of low power consumption and small size, and provide innovative solutions for the new architecture of chip systems in the post-Moore era.

XMC S-stacking^® Technology

XMC S-stacking^® technology enables direct bonding of two wafers in a vertical direction utilizing semiconductor nanoscale-interconnection technology.

In addition to significantly reducing chip size and achieving wafer-level interconnection, this technology can improve chip performance with faster I/O speed, higher bandwidth, lower latency and lower power consumption.

XMC S-stacking^® technology was successfully developed in 2016, till now XMC has accumulated world-leading mass production experience and technical capabilities. It has been successfully applied in computing, 3D depth sensors (ToF), 3D stacked memory and other fields, bringing excellent product performance and user experience to customers.

XMC M-stacking^® Technology

XMC M-stacking^® technology adopts a bumpless process to enable Cu-Cu interconnection of multiple wafers and lower interconnection resistance, which is a breakthrough over the traditional package-level Micro-bump interconnection architecture. This technology has achieved higher interconnection density and alignment accuracy with bonding yield of 99.5%.

Compared with traditional HBM, wafer-level stacking increases the bandwidth by 20 times and reduces the chip thickness by 40%.

XMC completed the process verification of three-wafer stacking technology at the end of 2018, and successfully developed five-wafer stacking process in 2020. XMC M-stacking^® technology provides a new solution for high-bandwidth products. This technology will provide more flexible and extensive options for applications such as data centers, in-storage computing, and IoT.

XMC Hi-stacking^® Technology

XMC is developing Hi-stacking^®(including 2.5D interposer), a 3D heterogeneous integration technology with more flexible design and process solutions.

Unlike traditional package-level interconnection architecture, XMC Hi-stacking^® technology can provide heterogeneous integration solutions for different die sizes or substrate materials, enabling stacking with more flexibility while achieving higher yield of stacked product and lower costs.

XMC 3D heterogeneous integration technology (Hi-stacking^®) can multiply the product’s memory density and communication bandwidth. It will serve the IoT, etc. markets that has a very high requirement for multi-module heterogeneous system integration with high-performance and low-power.